1. Field
The following description relates to a thin film transistor array panel and a manufacturing method thereof. More particularly, the description relates to a thin film transistor array panel and a manufacturing method for reducing skew formed during an etching process.
2. Discussion of the Background
A thin film transistor is used as a switching element to independently drive each pixel in a flat display device, such as a liquid crystal display or an organic light emitting device. The thin film transistor array panel including a thin film transistor may include a scanning signal line (or a gate line) to transmit a scanning signal to the thin film transistor and a data line that transmits a data signal, as well as a pixel electrode connected to the thin film transistor.
The thin film transistor may include a gate electrode that is connected to the gate line, a source electrode that is connected to the data line, a drain electrode that is connected to the pixel electrode, and a semiconductor layer. The semiconductor layer may be disposed on the gate electrode, which may be disposed between the source electrode and drain electrode. The data signal may be transmitted to the pixel electrode from the data line according to the gate signal from the gate line.
The semiconductor layer of the thin film transistor may be made of, without limitation, amorphous silicon, polysilicon (polycrystalline silicon), and a metal oxide.
Recently, an oxide semiconductor using a metal oxide having a lower cost and higher uniformity compared with polycrystalline silicon, as well as having a higher charge mobility and a higher ON/OFF ratio of a current compared with amorphous silicon has been researched.
If forming the oxide semiconductor of the semiconductor layer, the source electrode and the drain electrode may be formed by using a metal such as titanium (Ti) and copper (Cu).
If etching process is performed on an oxide semiconductor formed of titanium or copper by using a dry etching method, the etching rate may be below a reference threshold, such that a wet etching method may be used. Also, if etching process is performed on other materials other than the above described materials, the dry etching method may not be used in lieu of the wet etching to reduce its cost of operation.
If wet etching method is used in the etching process, isotropic etching may be performed, such that an etchant may penetrate into the metal layer positioned under a photosensitive film or a mask, and thereby a skew and/or an under-cut may be generated on side surfaces of the metal layer. Further, the etching process may not penetrate a semiconductor layer or any other layer disposed below the metal layer, such that boundaries the semiconductor layer protrudes beyond the skewed metal layer. In an example, the boundaries or ends of the semiconductor layer may protrude at least 0.5 um beyond the metal layer boundary. The protruded ends of the semiconductor layer may decrease the size of a design area, which may affect resolution quality of the display.
In a conventional 4-mask process, an etch-back process may be used to form the semiconductor layer, the source electrode, and the drain electrode using one mask. In the etch-back process, the photosensitive film may be etched such that a portion of the photosensitive film may be etched to provide a cavity or a channel portion in the photosensitive film to expose a portion of a layer including the source electrode and the drain electrode. In an example, etch back process may be performed on the photosensitive film with differing heights, such that the lower portion may be etched away to expose a portion of the metal layer while higher portions of the photosensitive film remains.
Accordingly, a boundary of the semiconductor layer and the boundary of the layer including the source electrode and the drain electrode may not correspond to each other. More specifically, edges of the layer including the source electrode and the drain electrode may be skewed, so that the semiconductor layer protrudes beyond the boundary of the layer including the source electrode and the drain electrode. However, the portion where the semiconductor layer that is protruded from the source electrode and the drain electrode may be unnecessary, and may cause a problem that a design margin must be increased.
The above information disclosed in this background section is only for enhancement of understanding of this disclosure and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.